// Copyright (C) 1953-2022 NUDT
// Verilog module name - local_tsmp_forward
// Version: V4.1.0.20221210
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module local_tsmp_forward
(
        i_clk,
        i_rst_n,
       
        iv_master_port                   ,
        iv_port_ptp_enabled              ,
        
        iv_ram_raddr        ,
        i_ram_rd            ,
        ov_ram_rdata        
);

// I/O
// clk & rst
input                     i_clk;                   //125Mhz
input                     i_rst_n;

input         [31:0]      iv_master_port;
input         [31:0]      iv_port_ptp_enabled;

input         [11:0]      iv_ram_raddr  ;
input                     i_ram_rd      ;
output reg    [33:0]      ov_ram_rdata  ;

always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        ov_ram_rdata           <= 34'h0;
    end                        
    else begin
	    if(i_ram_rd)begin
            if(iv_ram_raddr == 12'h0)begin
                ov_ram_rdata <= {1'b1,33'h1_0000_0000};
            end
            else if(iv_ram_raddr <= 12'h20)begin
                ov_ram_rdata <= {1'b1,33'd1 << (iv_ram_raddr - 1'b1)};
            end
            else if(iv_ram_raddr == 12'h700)begin//组播
                ov_ram_rdata <= iv_master_port;
            end
            else if(iv_ram_raddr == 12'h701)begin//组播
                ov_ram_rdata <= iv_port_ptp_enabled;
            end
            else begin
                ov_ram_rdata <= {1'b0,33'h0_0000_0000};
            end
        end
        else begin
            ov_ram_rdata           <= 34'h0;
        end
    end
end	
endmodule